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| HD74BC573A Octal D Type Transparent Latches With 3 State Outputs REJ03D0287-0300Z (Previous ADE-205-021A (Z)) Rev.3.00 Jul.16.2004 Description The HD74BC573A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features * Input/Output are at high impedance state when power supply is off. * Built in input pull up circuit can make input pins be open, when not used. * TTL level input * Wide operating temperature range Ta = -40 to + 85C * Ordering Information Part Name HD74BC573AP HD74BC573AFPEL Package Type DILP-20 pin Package Code DP-20N, -20NEV P FP Package Abbreviation -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity) SOP-20 pin (JEITA) FP-20DAV Note: Please consults the sales office for the above package availability. Function Table Output Control L L L H H L X Z Q0 : : : : : H H L X Latch Enable H L X X Data H L Q0 Z Output Q High leve Low level Immaterial High impedance Level of Q before the indicated steady input conditions were established Rev.3.00, Jul.16.2004, page 1 of 8 HD74BC573A Pin Arrangement Output Control 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q Latch Enable (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output voltage Off state output voltage Symbol VCC IIK VIN VOUT VOUT(off) Rating -0.5 to +7.0 30 -0.5 to +7.5 -0.5 to +7.5 -0.5 to +5.5 Unit V mA V V V Storage temperature Tstg -65 to +150 C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input voltage Output voltage Operating temperature Input rise/fall time*1 Note: Symbol VCC VIN VOUT Topr tr, tf 4.5 0 0 -40 0 Min 5.0 -- -- -- -- Typ 5.5 VCC VCC 85 8 Max V V V C ns/V Unit 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.3.00, Jul.16.2004, page 2 of 8 HD74BC573A Logic Diagram Output Control 1D DQ CK DQ CK 1Q 2D 2Q 7D DQ CK DQ CK 7Q 8D Latch Enable 8Q Electrical Characteristics (Ta = -40C to +85C) Item Input voltage Output voltage Symbol VIH VIL VOH VOL Input diode voltage Input current VIK II 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC (V) Min 2.0 -- 2.4 2.0 -- -- -- -- -- -- -100 -- -- -- -- -- -- Max -- 0.8 -- -- 0.4 0.5 -1.2 -250 1.0 100 -225 50 -50 29.5 2.5 2.5 1.5 Unit V V V V V V V A A A mA A A mA mA mA mA IOH = -3 mA IOH = -15 mA IOL = 24 mA IOL = 48 mA IIN = -18 mA VIN = 0 V VIN = 5.5 V VIN = 7.0 V VIN = 0 or 5.5 V VO = 2.7 V VO = 0.5 V VIN = 0 or 5.5 V All outputs is "L" VIN = 0 or 5.5 V All outputs is "H" VIN = 0 or 5.5 V All outputs is "Z" VIN = 3.4 or 0.5 V Test Conditions Short circuit output current* Off state output current Supply current 1 IOS IOZH IOZL ICCL ICCH ICCZ ICCT*2 Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. 2. When input by the TTL level, it shows ICC increase at per one input pin. Rev.3.00, Jul.16.2004, page 3 of 8 HD74BC573A Switching Test Method (CL = 50 pF) Ta = 25C VCC = 5.0 V Item Propagation delay time LE Q Output enable time Output disable time Setup time Hold time Pulse width Input capacitanse Output capacitance DQ Symbol Min tPLH 3.0 tPHL tPLH tPHL tZH tZL tHZ tLZ tS(H) tS(L) th(H) th(L) tw CIN CO 3.0 3.0 3.0 3.0 3.0 3.0 3.0 2.0 2.0 2.0 2.0 6.0 3.0 (Typ) 15.0 (Typ) Max 8.0 8.0 8.0 8.0 9.0 9.0 8.0 8.0 -- -- -- -- -- Ta = -40 to 85C VCC = 5.0 V 10% Min 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 2.0 2.0 2.0 2.0 6.0 -- -- Max 10.0 10.0 10.0 10.0 11.0 11.0 10.0 10.0 -- -- -- -- -- Unit Test conditions ns See under figure ns ns ns ns ns ns pF pF VIN = VCC or GND VO = VCC or GND Test Circuit VCC OC VCC Input Pulse Generator Zout = 50 Pulse Generator Zout = 50 See Function Table Output Input 1D to 8D 1Q to 8Q LE CL = 50 pF 500 450 50 Scope *2 OPEN 7V Notes: 1. CL includes probe and jig capacitance. 2. OPEN: tPLH, tPHL, tZH, tHZ, th, tS, tw 7 V: tZL, tLZ Rev.3.00, Jul.16.2004, page 4 of 8 HD74BC573A Waveforms-1 tr 90% 1.5 V 10% tr 90% Input D 10% t PLH 90% 10% t PHL 90% 1.5 V 10% tf 0V 3V tf 3V Input LE 0V VOH Output Q 1.5 V 1.5 V VOL Waveforms-2 tr 90% Input LE 10% tr 90% Input D 1.5 V 10% t PLH 90% 1.5 V 10% t PHL 0V VOH Output Q 1.5 V 1.5 V VOL tf 3V 3V 0V Rev.3.00, Jul.16.2004, page 5 of 8 HD74BC573A Waveforms-3 tr 90% 1.5 V 10% tw ts 90% 1.5 V 10% th 3V Input D 1.5 V 1.5 V 0V tf 3V Input LE 0V Notes: 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform: PRR =1 MHz, duty cycle 50% Waveforms-4 tf 90% 1.5 V 10% t ZL t LZ Waveform-A t ZH 1.5 V VOL + 0.3 V t HZ VOH - 0.3 V 1.5 V 0V VOH VOL 3.5 V tr 90% 1.5 V 10% 0V 3V Output Control Waveform-B Notes: 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform: PRR = 1 MHz, duty cycle 50% 3. Waveform-A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform-B shows input conditions such that the output is "H" level when enable by the output control. Rev.3.00, Jul.16.2004, page 6 of 8 HD74BC573A Package Dimensions As of January, 2003 Unit: mm 24.50 25.40 Max 20 11 1 0.89 1.27 Max 10 1.30 7.62 7.00 Max 2.54 Min 5.08 Max 0.51 Min 6.30 2.54 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 Package Code JEDEC JEITA Mass (reference value) DP-20N -- Conforms 1.26 g Unit: mm 24.50 25.40 Max 20 11 1 0.89 1.27 Max 10 1.30 7.62 7.00 Max 2.54 Min 5.08 Max 0.51 Min 6.30 2.54 0.25 *0.48 0.08 *0.25 0.06 0 - 15 *NI/Pd/AU Plating Package Code JEDEC JEITA Mass (reference value) DP-20NEV -- Conforms 1.26 g Rev.3.00, Jul.16.2004, page 7 of 8 HD74BC573A As of January, 2003 12.6 13 Max 20 Unit: mm 11 1 10 5.5 0.80 Max 2.20 Max *0.20 0.05 0.20 7.80 + 0.30 - 1.15 1.27 *0.40 0.06 0.10 0.10 0 - 8 0.70 0.20 0.15 0.12 M *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) FP-20DAV -- Conforms 0.31 g Rev.3.00, Jul.16.2004, page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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